Why is there a PLL in CPU? The Next CEO of Stack OverflowPLL - why compare phases not frequenciesCreating a clock multiplier using a PLLExample of a PLL for video genlockingWhat limits CPU speed?CPU and clock rateUsing CPU heat to generate electricityIs it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz CrystalWhy include frequency dividers in this PLL circuit?PLL placing fails on Lattice 5LP1K

How do scammers retract money, while you can’t?

What is the meaning of "rider"?

Can the Reverse Gravity spell affect the Meteor Swarm spell?

Is a stroke of luck acceptable after a series of unfavorable events?

'Given that' in a matrix

Return of the Riley Riddles in Reverse

Implement the Thanos sorting algorithm

Solution of this Diophantine Equation

Inappropriate reference requests from Journal reviewers

Unreliable Magic - Is it worth it?

Why does standard notation not preserve intervals (visually)

Under what conditions does the function C = f(A,B) satisfy H(C|A) = H(B)?

ls Ordering[Ordering[list]] optimal?

What's the point of interval inversion?

Why does GHC infer a monomorphic type here, even with MonomorphismRestriction disabled?

Are there languages with no euphemisms?

How can I quit an app using Terminal?

How to make a software documentation "officially" citable?

WOW air has ceased operation, can I get my tickets refunded?

I believe this to be a fraud

Number of words that can be made using all the letters of the word W, if Os as well as Is are separated is?

Customer Requests (Sometimes) Drive Me Bonkers!

How do I go from 300 unfinished/half written blog posts, to published posts?

What makes a siege story/plot interesting?



Why is there a PLL in CPU?



The Next CEO of Stack OverflowPLL - why compare phases not frequenciesCreating a clock multiplier using a PLLExample of a PLL for video genlockingWhat limits CPU speed?CPU and clock rateUsing CPU heat to generate electricityIs it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz CrystalWhy include frequency dividers in this PLL circuit?PLL placing fails on Lattice 5LP1K










3












$begingroup$


I read that PLL are used in CPU to generate the clock, but I can't understand why.



I don't really have any guess of why this is.










share|improve this question







New contributor




Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
Check out our Code of Conduct.







$endgroup$
















    3












    $begingroup$


    I read that PLL are used in CPU to generate the clock, but I can't understand why.



    I don't really have any guess of why this is.










    share|improve this question







    New contributor




    Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
    Check out our Code of Conduct.







    $endgroup$














      3












      3








      3





      $begingroup$


      I read that PLL are used in CPU to generate the clock, but I can't understand why.



      I don't really have any guess of why this is.










      share|improve this question







      New contributor




      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.







      $endgroup$




      I read that PLL are used in CPU to generate the clock, but I can't understand why.



      I don't really have any guess of why this is.







      clock cpu pll






      share|improve this question







      New contributor




      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.











      share|improve this question







      New contributor




      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.









      share|improve this question




      share|improve this question






      New contributor




      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.









      asked 2 hours ago









      Jonas DaverioJonas Daverio

      616




      616




      New contributor




      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.





      New contributor





      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.






      Jonas Daverio is a new contributor to this site. Take care in asking for clarification, commenting, and answering.
      Check out our Code of Conduct.




















          4 Answers
          4






          active

          oldest

          votes


















          4












          $begingroup$

          Been there, done that.



          Apart from other reasons mentioned here is a different one:

          The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.



          At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.

          The only way to do that is to use a PLL.



          Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.



          ++LEG is not a registered trademark. (At least as far as I know)






          share|improve this answer









          $endgroup$




















            3












            $begingroup$

            PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.






            share|improve this answer









            $endgroup$








            • 1




              $begingroup$
              Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
              $endgroup$
              – Sparky256
              2 hours ago


















            3












            $begingroup$

            PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.



            You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).



            Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.



            Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.






            share|improve this answer









            $endgroup$




















              2












              $begingroup$

              3 main reasons;



              1) power savings for mobiles and extend CPU life keeping cool.

              2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

              3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.



              Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.






              share|improve this answer









              $endgroup$













                Your Answer





                StackExchange.ifUsing("editor", function ()
                return StackExchange.using("mathjaxEditing", function ()
                StackExchange.MarkdownEditor.creationCallbacks.add(function (editor, postfix)
                StackExchange.mathjaxEditing.prepareWmdForMathJax(editor, postfix, [["\$", "\$"]]);
                );
                );
                , "mathjax-editing");

                StackExchange.ifUsing("editor", function ()
                return StackExchange.using("schematics", function ()
                StackExchange.schematics.init();
                );
                , "cicuitlab");

                StackExchange.ready(function()
                var channelOptions =
                tags: "".split(" "),
                id: "135"
                ;
                initTagRenderer("".split(" "), "".split(" "), channelOptions);

                StackExchange.using("externalEditor", function()
                // Have to fire editor after snippets, if snippets enabled
                if (StackExchange.settings.snippets.snippetsEnabled)
                StackExchange.using("snippets", function()
                createEditor();
                );

                else
                createEditor();

                );

                function createEditor()
                StackExchange.prepareEditor(
                heartbeatType: 'answer',
                autoActivateHeartbeat: false,
                convertImagesToLinks: false,
                noModals: true,
                showLowRepImageUploadWarning: true,
                reputationToPostImages: null,
                bindNavPrevention: true,
                postfix: "",
                imageUploader:
                brandingHtml: "Powered by u003ca class="icon-imgur-white" href="https://imgur.com/"u003eu003c/au003e",
                contentPolicyHtml: "User contributions licensed under u003ca href="https://creativecommons.org/licenses/by-sa/3.0/"u003ecc by-sa 3.0 with attribution requiredu003c/au003e u003ca href="https://stackoverflow.com/legal/content-policy"u003e(content policy)u003c/au003e",
                allowUrls: true
                ,
                onDemand: true,
                discardSelector: ".discard-answer"
                ,immediatelyShowMarkdownHelp:true
                );



                );






                Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.









                draft saved

                draft discarded


















                StackExchange.ready(
                function ()
                StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f429532%2fwhy-is-there-a-pll-in-cpu%23new-answer', 'question_page');

                );

                Post as a guest















                Required, but never shown

























                4 Answers
                4






                active

                oldest

                votes








                4 Answers
                4






                active

                oldest

                votes









                active

                oldest

                votes






                active

                oldest

                votes









                4












                $begingroup$

                Been there, done that.



                Apart from other reasons mentioned here is a different one:

                The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.



                At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.

                The only way to do that is to use a PLL.



                Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.



                ++LEG is not a registered trademark. (At least as far as I know)






                share|improve this answer









                $endgroup$

















                  4












                  $begingroup$

                  Been there, done that.



                  Apart from other reasons mentioned here is a different one:

                  The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.



                  At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.

                  The only way to do that is to use a PLL.



                  Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.



                  ++LEG is not a registered trademark. (At least as far as I know)






                  share|improve this answer









                  $endgroup$















                    4












                    4








                    4





                    $begingroup$

                    Been there, done that.



                    Apart from other reasons mentioned here is a different one:

                    The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.



                    At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.

                    The only way to do that is to use a PLL.



                    Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.



                    ++LEG is not a registered trademark. (At least as far as I know)






                    share|improve this answer









                    $endgroup$



                    Been there, done that.



                    Apart from other reasons mentioned here is a different one:

                    The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.



                    At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.

                    The only way to do that is to use a PLL.



                    Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.



                    ++LEG is not a registered trademark. (At least as far as I know)







                    share|improve this answer












                    share|improve this answer



                    share|improve this answer










                    answered 2 hours ago









                    OldfartOldfart

                    8,7512927




                    8,7512927























                        3












                        $begingroup$

                        PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.






                        share|improve this answer









                        $endgroup$








                        • 1




                          $begingroup$
                          Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                          $endgroup$
                          – Sparky256
                          2 hours ago















                        3












                        $begingroup$

                        PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.






                        share|improve this answer









                        $endgroup$








                        • 1




                          $begingroup$
                          Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                          $endgroup$
                          – Sparky256
                          2 hours ago













                        3












                        3








                        3





                        $begingroup$

                        PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.






                        share|improve this answer









                        $endgroup$



                        PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.







                        share|improve this answer












                        share|improve this answer



                        share|improve this answer










                        answered 2 hours ago









                        Dave TweedDave Tweed

                        122k9152264




                        122k9152264







                        • 1




                          $begingroup$
                          Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                          $endgroup$
                          – Sparky256
                          2 hours ago












                        • 1




                          $begingroup$
                          Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                          $endgroup$
                          – Sparky256
                          2 hours ago







                        1




                        1




                        $begingroup$
                        Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                        $endgroup$
                        – Sparky256
                        2 hours ago




                        $begingroup$
                        Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
                        $endgroup$
                        – Sparky256
                        2 hours ago











                        3












                        $begingroup$

                        PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.



                        You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).



                        Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.



                        Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.






                        share|improve this answer









                        $endgroup$

















                          3












                          $begingroup$

                          PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.



                          You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).



                          Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.



                          Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.






                          share|improve this answer









                          $endgroup$















                            3












                            3








                            3





                            $begingroup$

                            PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.



                            You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).



                            Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.



                            Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.






                            share|improve this answer









                            $endgroup$



                            PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.



                            You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).



                            Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.



                            Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.







                            share|improve this answer












                            share|improve this answer



                            share|improve this answer










                            answered 2 hours ago









                            Tom CarpenterTom Carpenter

                            39.9k375121




                            39.9k375121





















                                2












                                $begingroup$

                                3 main reasons;



                                1) power savings for mobiles and extend CPU life keeping cool.

                                2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

                                3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.



                                Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.






                                share|improve this answer









                                $endgroup$

















                                  2












                                  $begingroup$

                                  3 main reasons;



                                  1) power savings for mobiles and extend CPU life keeping cool.

                                  2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

                                  3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.



                                  Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.






                                  share|improve this answer









                                  $endgroup$















                                    2












                                    2








                                    2





                                    $begingroup$

                                    3 main reasons;



                                    1) power savings for mobiles and extend CPU life keeping cool.

                                    2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

                                    3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.



                                    Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.






                                    share|improve this answer









                                    $endgroup$



                                    3 main reasons;



                                    1) power savings for mobiles and extend CPU life keeping cool.

                                    2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance

                                    3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.



                                    Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.







                                    share|improve this answer












                                    share|improve this answer



                                    share|improve this answer










                                    answered 2 hours ago









                                    Sunnyskyguy EE75Sunnyskyguy EE75

                                    69.6k225101




                                    69.6k225101




















                                        Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.









                                        draft saved

                                        draft discarded


















                                        Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.












                                        Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.











                                        Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.














                                        Thanks for contributing an answer to Electrical Engineering Stack Exchange!


                                        • Please be sure to answer the question. Provide details and share your research!

                                        But avoid


                                        • Asking for help, clarification, or responding to other answers.

                                        • Making statements based on opinion; back them up with references or personal experience.

                                        Use MathJax to format equations. MathJax reference.


                                        To learn more, see our tips on writing great answers.




                                        draft saved


                                        draft discarded














                                        StackExchange.ready(
                                        function ()
                                        StackExchange.openid.initPostLogin('.new-post-login', 'https%3a%2f%2felectronics.stackexchange.com%2fquestions%2f429532%2fwhy-is-there-a-pll-in-cpu%23new-answer', 'question_page');

                                        );

                                        Post as a guest















                                        Required, but never shown





















































                                        Required, but never shown














                                        Required, but never shown












                                        Required, but never shown







                                        Required, but never shown

































                                        Required, but never shown














                                        Required, but never shown












                                        Required, but never shown







                                        Required, but never shown







                                        Popular posts from this blog

                                        Францішак Багушэвіч Змест Сям'я | Біяграфія | Творчасць | Мова Багушэвіча | Ацэнкі дзейнасці | Цікавыя факты | Спадчына | Выбраная бібліяграфія | Ушанаванне памяці | У філатэліі | Зноскі | Літаратура | Спасылкі | НавігацыяЛяхоўскі У. Рупіўся дзеля Бога і людзей: Жыццёвы шлях Лявона Вітан-Дубейкаўскага // Вольскі і Памідораў з песняй пра немца Адвакат, паэт, народны заступнік Ашмянскі веснікВ Минске появится площадь Богушевича и улица Сырокомли, Белорусская деловая газета, 19 июля 2001 г.Айцец беларускай нацыянальнай ідэі паўстаў у бронзе Сяргей Аляксандравіч Адашкевіч (1918, Мінск). 80-я гады. Бюст «Францішак Багушэвіч».Яўген Мікалаевіч Ціхановіч. «Партрэт Францішка Багушэвіча»Мікола Мікалаевіч Купава. «Партрэт зачынальніка новай беларускай літаратуры Францішка Багушэвіча»Уладзімір Іванавіч Мелехаў. На помніку «Змагарам за родную мову» Барэльеф «Францішак Багушэвіч»Памяць пра Багушэвіча на Віленшчыне Страчаная сталіца. Беларускія шыльды на вуліцах Вільні«Krynica». Ideologia i przywódcy białoruskiego katolicyzmuФранцішак БагушэвічТворы на knihi.comТворы Францішка Багушэвіча на bellib.byСодаль Уладзімір. Францішак Багушэвіч на Лідчыне;Луцкевіч Антон. Жыцьцё і творчасьць Фр. Багушэвіча ў успамінах ягоных сучасьнікаў // Запісы Беларускага Навуковага таварыства. Вільня, 1938. Сшытак 1. С. 16-34.Большая российская1188761710000 0000 5537 633Xn9209310021619551927869394п

                                        Беларусь Змест Назва Гісторыя Геаграфія Сімволіка Дзяржаўны лад Палітычныя партыі Міжнароднае становішча і знешняя палітыка Адміністрацыйны падзел Насельніцтва Эканоміка Культура і грамадства Сацыяльная сфера Узброеныя сілы Заўвагі Літаратура Спасылкі НавігацыяHGЯOiТоп-2011 г. (па версіі ej.by)Топ-2013 г. (па версіі ej.by)Топ-2016 г. (па версіі ej.by)Топ-2017 г. (па версіі ej.by)Нацыянальны статыстычны камітэт Рэспублікі БеларусьШчыльнасць насельніцтва па краінахhttp://naviny.by/rubrics/society/2011/09/16/ic_articles_116_175144/А. Калечыц, У. Ксяндзоў. Спробы засялення краю неандэртальскім чалавекам.І ў Менску былі мамантыА. Калечыц, У. Ксяндзоў. Старажытны каменны век (палеаліт). Першапачатковае засяленне тэрыторыіГ. Штыхаў. Балты і славяне ў VI—VIII стст.М. Клімаў. Полацкае княства ў IX—XI стст.Г. Штыхаў, В. Ляўко. Палітычная гісторыя Полацкай зямліГ. Штыхаў. Дзяржаўны лад у землях-княствахГ. Штыхаў. Дзяржаўны лад у землях-княствахБеларускія землі ў складзе Вялікага Княства ЛітоўскагаЛюблінская унія 1569 г."The Early Stages of Independence"Zapomniane prawdy25 гадоў таму было аб'яўлена, што Язэп Пілсудскі — беларус (фота)Наша вадаДакументы ЧАЭС: Забруджванне тэрыторыі Беларусі « ЧАЭС Зона адчужэнняСведения о политических партиях, зарегистрированных в Республике Беларусь // Министерство юстиции Республики БеларусьСтатыстычны бюлетэнь „Полаўзроставая структура насельніцтва Рэспублікі Беларусь на 1 студзеня 2012 года і сярэднегадовая колькасць насельніцтва за 2011 год“Индекс человеческого развития Беларуси — не было бы нижеБеларусь занимает первое место в СНГ по индексу развития с учетом гендерного факцёраНацыянальны статыстычны камітэт Рэспублікі БеларусьКанстытуцыя РБ. Артыкул 17Трансфармацыйныя задачы БеларусіВыйсце з крызісу — далейшае рэфармаванне Беларускі рубель — сусветны лідар па дэвальвацыяхПра змену коштаў у кастрычніку 2011 г.Бядней за беларусаў у СНД толькі таджыкіСярэдні заробак у верасні дасягнуў 2,26 мільёна рублёўЭканомікаГаласуем за ТОП-100 беларускай прозыСучасныя беларускія мастакіАрхитектура Беларуси BELARUS.BYА. Каханоўскі. Культура Беларусі ўсярэдзіне XVII—XVIII ст.Анталогія беларускай народнай песні, гуказапісы спеваўБеларускія Музычныя IнструментыБеларускі рок, які мы страцілі. Топ-10 гуртоў«Мясцовы час» — нязгаслая легенда беларускай рок-музыкіСЯРГЕЙ БУДКІН. МЫ НЯ ЗНАЕМ СВАЁЙ МУЗЫКІМ. А. Каладзінскі. НАРОДНЫ ТЭАТРМагнацкія культурныя цэнтрыПублічная дыскусія «Беларуская новая пьеса: без беларускай мовы ці беларуская?»Беларускія драматургі па-ранейшаму лепш ставяцца за мяжой, чым на радзіме«Працэс незалежнага кіно пайшоў, і дзяржаву турбуе яго непадкантрольнасць»Беларускія філосафы ў пошуках прасторыВсе идём в библиотекуАрхіваванаАб Нацыянальнай праграме даследавання і выкарыстання касмічнай прасторы ў мірных мэтах на 2008—2012 гадыУ космас — разам.У суседнім з Барысаўскім раёне пабудуюць Камандна-вымяральны пунктСвяты і абрады беларусаў«Мірныя бульбашы з малой краіны» — 5 непраўдзівых стэрэатыпаў пра БеларусьМ. Раманюк. Беларускае народнае адзеннеУ Беларусі скарачаецца колькасць злачынстваўЛукашэнка незадаволены мінскімі ўладамі Крадзяжы складаюць у Мінску каля 70% злачынстваў Узровень злачыннасці ў Мінскай вобласці — адзін з самых высокіх у краіне Генпракуратура аналізуе стан са злачыннасцю ў Беларусі па каэфіцыенце злачыннасці У Беларусі стабілізавалася крымінагеннае становішча, лічыць генпракурорЗамежнікі сталі здзяйсняць у Беларусі больш злачынстваўМУС Беларусі турбуе рост рэцыдыўнай злачыннасціЯ з ЖЭСа. Дазволіце вас абкрасці! Рэйтынг усіх службаў і падраздзяленняў ГУУС Мінгарвыканкама вырасАб КДБ РБГісторыя Аператыўна-аналітычнага цэнтра РБГісторыя ДКФРТаможняagentura.ruБеларусьBelarus.by — Афіцыйны сайт Рэспублікі БеларусьСайт урада БеларусіRadzima.org — Збор архітэктурных помнікаў, гісторыя Беларусі«Глобус Беларуси»Гербы и флаги БеларусиАсаблівасці каменнага веку на БеларусіА. Калечыц, У. Ксяндзоў. Старажытны каменны век (палеаліт). Першапачатковае засяленне тэрыторыіУ. Ксяндзоў. Сярэдні каменны век (мезаліт). Засяленне краю плямёнамі паляўнічых, рыбакоў і збіральнікаўА. Калечыц, М. Чарняўскі. Плямёны на тэрыторыі Беларусі ў новым каменным веку (неаліце)А. Калечыц, У. Ксяндзоў, М. Чарняўскі. Гаспадарчыя заняткі ў каменным векуЭ. Зайкоўскі. Духоўная культура ў каменным векуАсаблівасці бронзавага веку на БеларусіФарміраванне супольнасцей ранняга перыяду бронзавага векуФотографии БеларусиРоля беларускіх зямель ва ўтварэнні і ўмацаванні ВКЛВ. Фадзеева. З гісторыі развіцця беларускай народнай вышыўкіDMOZGran catalanaБольшая российскаяBritannica (анлайн)Швейцарскі гістарычны15325917611952699xDA123282154079143-90000 0001 2171 2080n9112870100577502ge128882171858027501086026362074122714179пппппп

                                        ValueError: Expected n_neighbors <= n_samples, but n_samples = 1, n_neighbors = 6 (SMOTE) The 2019 Stack Overflow Developer Survey Results Are InCan SMOTE be applied over sequence of words (sentences)?ValueError when doing validation with random forestsSMOTE and multi class oversamplingLogic behind SMOTE-NC?ValueError: Error when checking target: expected dense_1 to have shape (7,) but got array with shape (1,)SmoteBoost: Should SMOTE be ran individually for each iteration/tree in the boosting?solving multi-class imbalance classification using smote and OSSUsing SMOTE for Synthetic Data generation to improve performance on unbalanced dataproblem of entry format for a simple model in KerasSVM SMOTE fit_resample() function runs forever with no result