Why is there a PLL in CPU? The Next CEO of Stack OverflowPLL - why compare phases not frequenciesCreating a clock multiplier using a PLLExample of a PLL for video genlockingWhat limits CPU speed?CPU and clock rateUsing CPU heat to generate electricityIs it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz CrystalWhy include frequency dividers in this PLL circuit?PLL placing fails on Lattice 5LP1K
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Why is there a PLL in CPU?
The Next CEO of Stack OverflowPLL - why compare phases not frequenciesCreating a clock multiplier using a PLLExample of a PLL for video genlockingWhat limits CPU speed?CPU and clock rateUsing CPU heat to generate electricityIs it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?Maximum CPU Frequency of PIC24FJ256GA705 That I Can Get with 8MHz CrystalWhy include frequency dividers in this PLL circuit?PLL placing fails on Lattice 5LP1K
$begingroup$
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
clock cpu pll
New contributor
$endgroup$
add a comment |
$begingroup$
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
clock cpu pll
New contributor
$endgroup$
add a comment |
$begingroup$
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
clock cpu pll
New contributor
$endgroup$
I read that PLL are used in CPU to generate the clock, but I can't understand why.
I don't really have any guess of why this is.
clock cpu pll
clock cpu pll
New contributor
New contributor
New contributor
asked 2 hours ago
Jonas DaverioJonas Daverio
616
616
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New contributor
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add a comment |
4 Answers
4
active
oldest
votes
$begingroup$
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.
At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.
Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.
++LEG is not a registered trademark. (At least as far as I know)
$endgroup$
add a comment |
$begingroup$
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.
$endgroup$
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
add a comment |
$begingroup$
PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.
You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).
Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.
Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.
$endgroup$
add a comment |
$begingroup$
3 main reasons;
1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.
Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.
$endgroup$
add a comment |
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4 Answers
4
active
oldest
votes
4 Answers
4
active
oldest
votes
active
oldest
votes
active
oldest
votes
$begingroup$
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.
At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.
Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.
++LEG is not a registered trademark. (At least as far as I know)
$endgroup$
add a comment |
$begingroup$
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.
At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.
Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.
++LEG is not a registered trademark. (At least as far as I know)
$endgroup$
add a comment |
$begingroup$
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.
At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.
Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.
++LEG is not a registered trademark. (At least as far as I know)
$endgroup$
Been there, done that.
Apart from other reasons mentioned here is a different one:
The marketing guys want to make the chip design as cheap as possible. Thus they prefer to use cheap crystals. The ones use for Ethernet fall in that category. So you often end up having to use a 25MHz crystal.
At the same time marketing want powerful processors. Thus the processor (Let's call it a LEG++) should be able to run at 1 or 2 GHz.
The only way to do that is to use a PLL.
Or the processor can run at max 64MHz, but they want to have a USB interface which requires a 48MHz Clock. Again PLL to the rescue.
++LEG is not a registered trademark. (At least as far as I know)
answered 2 hours ago
OldfartOldfart
8,7512927
8,7512927
add a comment |
add a comment |
$begingroup$
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.
$endgroup$
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
add a comment |
$begingroup$
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.
$endgroup$
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
add a comment |
$begingroup$
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.
$endgroup$
PLLs can be used to multiply and divide frequencies. CPUs that have PLLs to generate their clocks are highly reconfigurable. The clock speed can be varied relative to the external reference clock over a wide range, and it's the PLL that makes this possible.
answered 2 hours ago
Dave Tweed♦Dave Tweed
122k9152264
122k9152264
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
add a comment |
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
1
1
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
$begingroup$
Also it is not possible to get xtals to oscillate much beyond 100MHZ, so the ref oscillator needs to be multiplied many times to get 1 GHZ to 4 GHZ core frequencies. Core frequency is usually a integer multiple of the ref xtal.
$endgroup$
– Sparky256
2 hours ago
add a comment |
$begingroup$
PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.
You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).
Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.
Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.
$endgroup$
add a comment |
$begingroup$
PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.
You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).
Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.
Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.
$endgroup$
add a comment |
$begingroup$
PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.
You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).
Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.
Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.
$endgroup$
PLLs are used primarily to generate one or more faster or slower clocks from a reference clock.
You might have say a fixed 100MHz crystal, but then want to run your CPU at 2GHz, so a PLL is required to increase the frequency (a 2GHz clock crystal isn't feasible).
Additional you may want to be able to change your CPU frequency on the fly (e.g. a turbo clock). In which case you could have a reconfigurable PLL.
Furthermore you may need a different memory or peripheral clock to your CPU clock. Again a PLL and divider can be used to generate this from a single reference.
answered 2 hours ago
Tom CarpenterTom Carpenter
39.9k375121
39.9k375121
add a comment |
add a comment |
$begingroup$
3 main reasons;
1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.
Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.
$endgroup$
add a comment |
$begingroup$
3 main reasons;
1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.
Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.
$endgroup$
add a comment |
$begingroup$
3 main reasons;
1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.
Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.
$endgroup$
3 main reasons;
1) power savings for mobiles and extend CPU life keeping cool.
2) signal integrity is improved using xx multiplier for front side bus due to short wavelength, lower capacitance
3) flexible CPU speeds are possible with throttle on Clock multiplier and Vdd to allow burst CPU power and cool down.
Signal routing of 100MHz FSB is easy, > 1GHz is hard and your CPU is much higher, driver current increases with f and standing wave reflections distort square waves. While reducing CPU clock saves power and reduces temp.
answered 2 hours ago
Sunnyskyguy EE75Sunnyskyguy EE75
69.6k225101
69.6k225101
add a comment |
add a comment |
Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.
Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.
Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.
Jonas Daverio is a new contributor. Be nice, and check out our Code of Conduct.
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